1. Field of the Invention
The present invention relates to forming metallized patterns on the top surface of high density printed circuit boards (PCBs) and particularly to forming metallized features on multilayer printed circuit boards having electrically conductive through-holes that open to an external surface.
2. Description of the Related Art
Multilayer printed circuit boards, including the high density type, include several electrically conductive layers separated by layers of dielectric material. Some of these conductive layers are utilized as power planes while other conductive layers may be patterned for electrical signal connections (e.g. between integrated circuit chips). Multilayer circuit board constructions are manufactured by combining a plurality of smaller, independently formed circuit board structures termed "core assemblies" or just "cores". The manufacturing process for each core includes etching predetermined conductive layers in a predetermined pattern and laminating them together to form a core assembly. Each core assembly is manufactured and tested separately before being laminated into a multilayer structure with the other cores. The finished core assemblies are aligned and then laminated together in a complex process that includes application of heat and pressure to close gaps created by accumulated process and material tolerances, and to assure intimate contact for all through-holes and mechanical bonding of the external dielectric layers.
In those situations where electrical interconnections are desired between adjacent conducting layers, it has been common in the art to provide such connections with "plated-through-holes" (PTHs), sometimes referred to as "through-holes" or "vias". Conventionally, through-holes are formed only after the cores have been laminated to form a complete multilayer structure, by drilling an aperture in the multilayer structure and electro-plating the interior to electrically connect the conductive layers through which the through-hole has been drilled. In an improved process, such as described in U.S. Pat. No. 5,359,797, to Chen, et al., the through-holes are formed separately in each core before forming a multilayer structure by drilling an aperture in each core and then electro-plating the interior and an area surrounding the opening to form a conductive through-hole and via lands. When the core assemblies are aligned to prepare for lamination, the apertures in each core become aligned to define a through-hole. After lamination, the through-holes formed in the multilayer structure can extend through multiple cores, and sometimes open on the top external surface, the bottom external surface, or both of the external surfaces of the multilayer structure. As used herein, the term "through-hole" is meant to include all types of through-holes and vias, including PTHs that open to an external surface.
Multilayer electronic structures require a plurality of mounting sites or pads formed on one or both external surfaces, which are used for mounting an electronic device such as a semiconductor chip to the multilayer circuit board. Particularly, the mounting structures provide a way for the electronic device to connect with signal lines, power planes, and any other structures in the multilayer circuit board. The mounting sites comprise an electrically conductive material and have a predetermined pattern to function as ground, power, and/or signal sites, for example. Usually, the pattern of mounting sites is designed to match the pattern of power, ground, or signal sites on the attached device. Frequently, the mounting sites are electrically connected to plated through-holes that open externally from the multilayer circuit board.
As the dimensions of electrical circuit components have been reduced, the density of the ground, power, and signal sites on the chip to be attached to a printed circuit board (or card or chip carrier) have also increased. This increased density of the components to be attached unfortunately requires increased density on the mounting surface of the circuit board. For example, direct chip attachment methods may require the pads to which they attach to be on a very fine area array pitch (e.g. 8 mil center-to-center spacing between pads). Another example of an instance where a fine array pitch may be required is a high I/O module.
The presence of a through-hole opening in a circuit board can cause problems while connecting the component to the circuit board, including wicking of the molten solder into the metallized through-hole. One result of such wicking is reduced solderball volume, which unfavorably decreases assembly yield and interconnect reliability.
If the component grid is large enough, the wicking problem can be solved by elongating the via land, or utilizing a `dogbone` shaped pad in conjunction with a soldermask, to provide an assembly pad physically isolated from the via yet electrically commoned to it. As a result the mounting (or assembly) pad is offset from the through-hole grid.
However, where the component grid is very fine, there may be no available space to offset the mounting pad. In other words, a very fine grid may not have sufficient space to resolve circuitized features interstitially, nor to resolve the soldermask image necessary to `dam` solder away from the vias. Particularly in these instances, a method is needed to form solder interconnections between the component and carrier directly above (rather than offset from) these through-holes. Arranging the mounting pads directly over the drilled holes provides a maximum density of input and output sites and eliminates the need for a solder mask. However, placing solder balls or mounting chips directly over through-holes, or even close thereto, requires a method for plugging the through-holes to prevent solder from wicking away from the joint and into the through-hole to avoid the wicking problem.
Kamperman, in U.S. patent application Ser. No. 08/352,144, filed Dec. 1, 1994, discloses a method for capping externally-opening through-holes in multilayer structures. Kamperman discloses first depositing a bonding metal on a copper layer in a predetermined pattern that matches the through-hole openings, and then bonding the metal to the multilayer structure, including covering the externally-opening through-holes. Finally, the copper layer in the multilayer structure is etched in a predetermined pattern for the purpose of providing mounting sites for components or other structures.
This final step unfortunately increases part cost by reducing the yield of a (by now) very expensive composite multilayer structure. The more complex the pattern to resolve on the surface, the greater the yield loss will be. For example, the yield loss of this final step could be 10% for some high density patterns. Furthermore, the entire nearly completed multilayer structure is subjected to potentially damaging chemical intrusion and mechanical stresses. If damaged, the part must be thrown away, and yield decreases accordingly.
Another disadvantage of the process disclosed by Kamperman et al. is that, because the copper layer is in place during lamination and cannot extend below the external dielectric surface adjacent to it and the copper layer forms part of the final pad, the pad cannot be formed flush with the external dielectric surface.